This application claims priority to Ser. No. 99400558.5, filed in Europe on Mar. 8, 1999 and Ser. No. 98402455.4, filed in Europe on Oct. 6, 1998.
The present invention relates to processors, and to emulation of a processor for debugging hardware or software.
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. It is known to provide a stack that can be used to pass variables from one software routine to another. Stacks are also used to maintain the contents of the program counter when a first software routine calls a second software routine, so that program flow can return to the first software routine upon completion of the called second routine. A call within the second software routine can call a third routine, etc. Furthermore, it is known to provide a software breakpoint instruction to be used during software debugging.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as mobile telecommunications applications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a processor that is a programmable digital signal processor (DSP), offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit operable to decode an instruction fetched from an instruction memory. The instruction may have a number of instruction format lengths. The processor also has a data computation unit for executing the instructions decoded by the instruction buffer unit and a program counter operable to provide an instruction address that is provided to the instruction memory. The instruction buffer unit is operable to decode a software breakpoint instruction (SWBP) having a length equal to any of the instruction length formats of the instruction set.
In accordance with another aspect of the present invention, the instruction buffer is operable to decode a software breakpoint instruction combined with a non-operational instruction in a single cycle such that the combined software breakpoint instruction and the non-operational instruction (NOP) are treated as a single instruction by the data computation unit.
In accordance with another aspect of the present invention, the software breakpoint instruction has a small number of instruction length formats which is less than the number of instruction length formats in the complete instruction set. However, for the combination of SWBP and NOP instruction, there is a combined instruction length format to match each instruction length format of the instruction set.
In accordance with another aspect of the present invention, a method of operating a digital system is provided. A plurality of instructions are executed in an instruction pipeline of the processor core, wherein the instructions are fetched in response to a program counter from an instruction memory associated with the processor core, wherein the sequence of instructions are selected from an instruction set having a number of instruction length formats. During emulation, an instruction in the sequence of instructions is replaced with a software breakpoint instruction having the same instruction length format as the instruction it replaces, regardless of length. The execution sequence is broken by executing the software breakpoint instruction after executing a portion of the sequence of instructions. Then, execution of the sequence of instructions is resumed by replacing the software breakpoint instruction with the previously replaced instruction in the sequence of instructions.
Another aspect of the present invention is that the first software breakpoint instruction is formed by selecting a one of a few software breakpoint instruction and combining the software breakpoint instruction with non-operational instruction such that the combined length of the software breakpoint instruction and the non-operational instruction is equal to the instruction length of the replaced instruction.
Another aspect of the present invention is that when a software breakpoint instruction is executed in a delay slot resulting from executing a discontinuity type instruction, a return address is stored with the same value as if the replaced instruction where present in the sequence of instructions.